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# 物理代写|模拟电路代写Analog Circuit代考|ECE511 Optimization Algorithm of Choice: Simulated Annealing

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## 物理代写|模拟电路代写Analog Circuit代考|Optimization Algorithm of Choice: Simulated Annealing

SA [5] is one of the most popular stochastic techniques, and is used in most of the optimization-based floorplan approaches for analog design automation proposed in the last decades. SA is a stochastic point-to-point search method that draws analogy from annealing of solids. Without the loss of generality it is assumed that in a minimization problem the current solution $u$ is moved to a neighbor $v$, which can be accepted according to the probability $p(f(u), \mathrm{f}(v))$ :
$$p(f(u), f(v))=\frac{1}{1+e^{\left[(f(u)-f(v)) /\left(T^* f(u)\right)\right]}}$$
where $\mathrm{f}(u)$ and $\mathrm{f}(v)$ are the relative performances of the current and neighbor solutions. The probability can be a more flat or a more abrupt function of the relative performance, this is controlled with the parameter $T$, which commonly scheduled as an exponentially decreasing function of time:
$$T(t)=T_{\max } \cdot e^{-R \cdot\left(\frac{t}{k}\right)}$$
where $R$ is the temperature decreasing rate, $k$ a scale factor for the iteration counter $t$ and $T_{\max }$ is the initial temperature. For high values of $T$, the probability $p$ gets flat around $50 \%$, i.e., explore the solution space, and for low values of $T$, the probability $p$ can be approximately given by Eq. (2.4), i.e., exploit.
$$p(f(u), f(v))=\left{\begin{array}{l} 1 \text { when } f(v)<f(u) \ 0 \text { when } f(v) \geq f(u) \end{array}\right.$$
This way, SA is capable of accepting unfavorable solutions probabilistically. The use of stochastically controlled hill-climbing allows SA to avoid local minima during the optimization process.

## 物理代写|模拟电路代写Analog Circuit代考|Commercial Solutions

Recently, some commercial solutions have emerged in the analog layout EDA market. Tanner EDA [48] HiPer DevGen, acquired by Mentor Graphics’ , presents a smart generator to accelerate the creation of standard cells. The tool analyzes the netlist and recognizes the current mirrors and differential pairs, and then automatically sends them to the generators. The generated primitives intend to be similar to those handcrafted, where designers have the control over the generation options, i.e., placement and routing of these structures. For differential pairs there are multiple options to ensure matching, optimized parasitic, add dummy devices, guard rings, antenna effect diodes, etc. For current mirrors there are multiple outputs of different electric-current strengths, options to ensure matching, add dummy devices, share diffusion, multiple finger with options for gate and bulk connections, and adjustments for well proximity effects. To configure a new technology only the design rules are required to have design-rule correct and layout-versus-schematic verified standard cells.

Synopsys ${ }^{\circledast}$ Helix $^{\mathrm{TM}}[49]$ is a placement manager supported by a powerful and easy to use graphical user interface (GUI). The designer introduces the system hierarchy and each of the sub-blocks can be added independently from the remaining. This perspective is useful on an on-going system-level specifications translation, since the parasitics of the available blocks and estimated areas can be provided for the designer to optimize the system-level design. For the automatic placement, the designer provides a set of constraints for a given circuit schematic and the tool automatically presents a set of possible minimum-spacing layout alternatives for that block. The tool explores the possible combinations deterministically and produces design-rule correct placement solutions for modern technology design processes. The output is a standard OpenAccess database that can be edited in most of the layout editors.

## 物理代写|模拟电路代写ANALOG CIRCUIT代考|OPTIMIZATION ALGORITHM OF CHOICE: SIMULATED ANNEALING

$$5$$

$$p(f(u), f(v))=\frac{1}{1+e^{\left[(f(u)-f(v)) /\left(T^* f(u)\right)\right]}}$$

$$T(t)=T_{\max } \cdot e^{-R \cdot\left(\frac{t}{k}\right)}$$

$\$ \$$对 f(u, F v)= 左 { 1 when f(v)<f(u) 0 when f(v) \geq f(u) 正确的。 \ \$$

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