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电子工程代写|电路设计作业代写Intro to circuit design代考|Existing Approaches to Automatic Layout Generation

如果你也在 怎样代写电路设计Intro to circuit design这个学科遇到相关的难题,请随时右上角联系我们的24/7代写客服。电路设计Intro to circuit design一个简单的电路由电阻器、电容器、电感器、晶体管、二极管和集成电路组成。这些基本的电子元件是由导电线连接的。电流可以很容易地在这些导线之间流动,以便使电子元件处于工作状态。

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电子工程代写|电路设计作业代写Intro to circuit design代考|Existing Approaches to Automatic Layout Generation

电子工程代写|电路设计作业代写Intro to circuit design代考|Layout Generation with Placement and Routing Constraints

This methodology does not use any information from previously designed layouts; instead, every solution is generated from scratch. To reduce the unpredictability of the time-consuming optimization process and produce a solution meaningful for the designer, usually, a high amount of topological constraints and objectives are set. The first step of this layout synthesis methodology consists on generating the devices required on the circuit, i.e., module instantiation, creating an independent layout of each device and/or group of devices, including the internal routing. The second step consists of placing those devices on the floorplan while respecting the topological constraints and achieving the minimum layout area and/or desired aspect ratio. One of the most relevant factors when developing a placement tool is its representation of the cells internally, and each tool has its own strategy for it. The two main classes of approaches that have been used in the last years are distinguished by how the optimizer encodes and moves those cells [14]: by absolute representation, i.e., cells are represented by means of absolute coordinates 15-21; and, by means of a relative representation, i.e., encoding the positioning relations between any pair of cells, the last one can further classified into slicing 22 or non-slicing representations, e.g., sequence pair 23, ordered tree $[24,25], B^{*}$-tree [26-28], transitive closure graphbased 29-32, or HB *-tree 33-35. The placement result is commonly achieved using an optimization-based approach, being simulated annealing algorithm 36the most common optimization kernel used. Finally, the interconnections between devices are drawn respecting the routing constraints and minimizing the total wiring length. This process is usually performed with traditional path-finding algorithms, e.g., classic maze algorithm [37] or line-expansion techniques [16]; however, fully stochastic approaches were also proposed 38-40 The major disadvantage of this approach is that the result of it is ultimately unpredictable, and therefore, the output can be meaningful for the designer or not.

电子工程代写|电路设计作业代写Intro to circuit design代考|Layout Migration and Retargeting

Since the layouts generated using optimization and considering several constraints for placement and routing may still not exactly reproduce major designers’ intents, some studies synthesize analog layouts based on layout migration or layout retargeting from legacy data. Layout retargeting is the process of generating a layout from an existing layout. The main target is to conserve most of the design choices and knowledge of the source design, while migrating it another given technology; update specifications; or attempt to optimize the old design. To synthesize the new layout with new devices’ size and process technology, the previously designed layout topology is kept since it contains the designers’ knowledge and the layout design preferences. Therefore, there is no need to design the entire layout from scratch. Using a qualified analog layout as the basis for a new one ensures the topology and some layout constraints are kept such as symmetry and proximity. The new layout can be generated using compaction techniques such as linear programming or graph-based algorithms that minimize the layout area and satisfy the set of placement and routing constraints $[41,42]$. The migration or retargeting can also be performed using the so-called template-based approaches $[8,43]$. In the latest, a technologyand specification-independent template is created by the designer, and then, that template is used for different devices’ sizes and/or technologies. As major drawbacks, a single template or legacy layout hardly yields compact placement solutions for the multitude of different sizing solutions that can be provided for the same circuit, and also, the development of a placement template can be as time-consuming as manually designing the placement itself. In $[44,45]$, a methodology that combines layout generation considering placement and routing constraints and layout migration or retargeting was proposed, by generating placement templates through an optimization process.

电子工程代写|电路设计作业代写INTRO TO CIRCUIT DESIGN代考|Layout Synthesis with Knowledge Mining

More recently, a knowledge-based methodology that generates new layouts by integrating existent design expertise was proposed in $[46,47]$. The approach automatically analyzes legacy design data including schematics, layouts, and constraints and generates multiple layouts for the new design by reutilizing the legacy information. In summary, layout synthesis with knowledge mining consists in four major steps: (1) analysis of the legacy design data including circuits, layouts, and constraints; (2) construction of design knowledge database resulting from the analysis of legacy designs; (3) extraction of matched subcircuits between new and legacy designs; and (4) generation of the feasible layouts for the new design by utilizing the qualityapproved legacy layouts of matched subcircuits in the design knowledge database. Unlike layout migration or retargeting from a previous legacy design or template, here a small number of legacy layouts from different circuit topologies are used.

However, since graph representations are built for each legacy layout, and then, the solution being produced matches its subcircuits with those found on the legacy graphs, the conflicts are deterministically solved, as the acquired “knowledge” is not generalized but only applied.

电子工程代写|电路设计作业代写Intro to circuit design代考|Existing Approaches to Automatic Layout Generation



该方法不使用来自先前设计布局的任何信息;相反,每个解决方案都是从头开始生成的。为了减少耗时的优化过程的不可预测性并产生对设计者有意义的解决方案,通常会设置大量的拓扑约束和目标。这种布局综合方法的第一步包括生成电路所需的器件,即模块实例化,创建每个器件和/或器件组的独立布局,包括内部布线。第二步包括将这些设备放置在平面图上,同时尊重拓扑约束并实现最小布局面积和/或所需的纵横比。开发放置工具时最相关的因素之一是其内部单元格的表示,并且每个工具都有自己的策略。过去几年使用的两大类方法的区别在于优化器如何编码和移动这些单元格14:通过绝对表示,即单元格用绝对坐标15-21表示;并且,通过相对表示,即编码任意一对cell之间的定位关系,最后一个可以进一步分为slicing 22或non-slicing表示,例如sequence pair 23,有序树[24,25],乙∗-树26−28,基于图的传递闭包 29-32,或 HB *-tree 33-35。放置结果通常使用基于优化的方法来实现,模拟退火算法 36 是最常用的优化内核。最后,根据布线约束和最小化总布线长度绘制设备之间的互连。这个过程通常使用传统的寻路算法来执行,例如经典的迷宫算法37或行扩展技术16; 然而,也提出了完全随机的方法 38-40 这种方法的主要缺点是它的结果最终是不可预测的,因此,输出对设计师来说可能有意义,也可能没有意义。


由于使用优化生成的版图并考虑了布局和布线的几个约束可能仍然不能完全再现主要设计人员的意图,因此一些研究基于版图迁移或从遗留数据重新定位的版图来综合模拟版图。布局重定向是从现有布局生成布局的过程。主要目标是保留源设计的大部分设计选择和知识,同时将其移植到另一种给定技术;更新规格;或尝试优化旧设计。为了将新版图与新器件的尺寸和工艺技术相结合,保留了先前设计的版图拓扑,因为它包含了设计人员的知识和版图设计偏好。因此,无需从头开始设计整个布局。使用合格的模拟布局作为新布局的基础,可确保保持拓扑结构和一些布局约束,例如对称性和接近性。可以使用压缩技术(例如线性编程或基于图形的算法)生成新的布局,以最小化布局面积并满足布局和布线约束集[41,42]. 迁移或重定向也可以使用所谓的基于模板的方法来执行[8,43]. 最近,设计者创建了一个独立于技术和规范的模板,然后,该模板用于不同的设备尺寸和/或技术。作为主要缺点,单个模板或旧版布局很难为同一电路提供多种不同尺寸的解决方案提供紧凑的布局解决方案,而且布局模板的开发可能与手动设计布局一样耗时。安置本身。在[44,45],通过优化过程生成布局模板,提出了一种结合布局生成考虑布局和布线约束以及布局迁移或重新定位的方法。


最近,在[46,47]. 该方法自动分析包括原理图、布局和约束在内的遗留设计数据,并通过重新利用遗留信息为新设计生成多个布局。总之,知识挖掘的布局综合包括四个主要步骤:1分析遗留设计数据,包括电路、布局和约束;2通过对遗留设计的分析,构建设计知识数据库;3提取新旧设计之间的匹配子电路;和4通过利用设计知识数据库中匹配子电路的质量认可的传统布局,为新设计生成可行的布局。与以前的传统设计或模板的布局迁移或重新定位不同,这里使用了来自不同电路拓扑的少量传统布局。


电子工程代写|电路设计作业代写Intro to circuit design代考

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